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DR8051
8-bit RISC Microcontroller ver 2.00
OVERVIEW
DR8051 soft core is binary-compatible with the industry standard 8051 8-bit microcontroller and can achieve a performance of up to 55 million instructions per second in today's integrated circuit technologies. DR8051 has RISC architecture that is 6.7 time faster compare to the original implementation. User programmable RAMWE and RAMRD pulses between 1 to 8 clock periods De-multiplexed Address/Data Bus to allow easy connection to memory Over 16 times data transfer faster than the original implementation Two 16-bit timer/counters Full-duplex serial port Support for External SFRs Fully synthesizable, static synchronous design with no internal tri-states 1 GHz virtual clock frequency compare to the original implementation (over 150 MHz in a typical 0.25u technological process)
KEY FEATURES
Software compatible with industry standard 8051 RISC architecture 6.7 times faster than the original implementation 4-clk periods multiplication 5-clk periods division Up to 16M bytes of external standard Data Memory Up to 256 bytes of internal dual port Data Memory Up to 64K bytes of Program Memory
SPECIAL FEATURES
I2C bus controller Floating-Point arithmetic coprocessor IEEE-754 standard single precision u FADD, FSUB - addition, subtraction u FMUL, FDIV- multiplication, division u FSQRT- square root
u FUCOM - compare u FCHS - change sign u FABS - absolute value Floating-Point math coprocessor - IEEE754 standard single precision real, word and short integers u FADD, FSUB- addition, subtraction u FMUL, FDIV- multiplication, division u FSQRT- square root u FUCOM- compare u FCHS - change sign u FABS - absolute value u FSIN, FCOS- sine, cosine u FPTAN, FPATAN- tangent, arcs tangent Allows applications software to access up to 16 MB of external data memory. Extra DPP( Data Page Pointer) register is used for segments swapping. Up to 104 External Special Function Registers (ESFRs) may be added to the DR8051 design. ESFRs are memory mapped into Direct Memory between addresses 80 hex and FF hex in the same manner as core SFRs and may occupy any address that is not occupied by a core SFR.
u STRETCH MEMORY CYCLE REGISTER:
Allows applications software to adjust to different external RAM speeds (XRAMWR and XRAMRD pulse between 1 - 8 clock cycles).
u EXTERNAL RAM:
DELIVERABLES
VHDL, Verilog source code VITAL simulation model HDL test bench Synthesis scripts Technical documentation Technical support
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
SYMBOL
prgdata(7:0) prgaddr(15:0) xramdatai(7:0) xramdatao(7:0) xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramsfrdatao(7:0) sfrdatai(7:0) ramsfraddr(7:0) int0 int1 t0 gate0 t1 gate1 rxdi rst clk ramrd ramwe sfrrd sfrwe
DESIGN FEATURES
u DATA MEMORY:
The DR8051 can address Internal Data Memory of up to 256 bytes, and up to 16M bytes of external Data RAM via the function interconnect signals. The Internal Data Memory can be implemented as Single-Port synchronous or asynchronous RAM.
u EXTERNAL SPECIAL FUNCTION REGISTERS:
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rxdo txd
PINS DESCRIPTION
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PIN
clk rst port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] prgdata[7:0] xramdatai[7:0] ramdati[7:0] sfrdatai[7:0] int0 int1 t0 t1 gate0 gate1 rxdi port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] prgaddr[15:0] xramaddr[23:0] xramdatao[7:0] xramwr xramrd ramsfraddr[7:0] ramwe ramrd sfrwe sfrrd rxdo txd
TYPE
input input input input input input input input input input input input input input input input input
DESCRIPTION
Global clock Global reset Port 0 input Port 1 input Port 2 input Port 3 input Data bus from program memory Data bus from ext. data memory Data bus from int. data memory Data bus from user SFR's External interrupt 0 External interrupt 1 Timer 0 input Timer 1 input Timer 0 gate input Timer 1 gate input Serial receiver input
The following table gives a survey about the DR8051 performance in ALTERA(R) devices after Place & Route (all key features have been included): a) FLEXTM 10K100E-1 Area - 2049 LC + 1EAB System clock fmax - 58 MHz b) APEXTM 20K100E-1 Area - 2120 LC System clock fmax - 58 MHz c) ACEXTM 1K100-1 Area - 2096 LC + 1 EAB System clock fmax - 57 MHz
output Port 0 output output Port 1 output output Port 2 output output Port 3 output output Program memory address bus output External data memory address bus output Data bus for external data memory output External data memory write output External data memory read output RAM and SFR's address bus output Internal data memory write enable output Internal data memory read output User SFR's write enable output User SFR's read output Serial receiver output output Serial transmitter output
ramsfrdatao[7:0] output Data bus for internal data memory
PERFORMANCE
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MODIFICATIONS
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Copyright 1999-2000 DCD - Digital Core Design. All Rights Reserved.
For any modification or special request contact to DCD. Headquarter: Wroclawska 94 41-902 Bytom POLAND e-mail: info@dcd.com.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37
Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245 USA e-mail: info-us@dcd.com.pl tel. fax : +1 210 667 0185 : +1 210 667 0635
Distributor: MTC-Micro Tech Consulting GmbH AM Weidegrund 10 D-82194 Grobenzell Germany e-mail : MTCinfo@mtc.de tel. fax : +49 8142 5961-0 : +49 8142 5961-44
All trademarks mentioned in this document are trademarks of their respective owners.
http://www.dcd.com.pl
Copyright 1999-2000 DCD - Digital Core Design. All Rights Reserved.

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